Data processing has always relied on peripheral storage units such as magnetic tape units and magnetic disk units for storing large amounts of data. Data from such paripheral storage units have been transferred on a demand basis to a main memory of the data processing unit such as shown by Kilburn, et al in U.S. Pat. Nos. 3,217,298 and 3,218,611. In these instances the main memory was used to queue the data awaiting use by the computer programs which required the data. The notion of enhanced performance of a peripheral storage device through the use of data buffers is set forth by Gregory, et al, U.S. Pat. No. 2,960,683. Gregory, et al teach that data can be queued in a first in first out (FIFO) buffer interposed between a peripheral data recorder and a data processing main memory. The effect of the Gregory, et al data buffer is to tend to mask the mechanical delays of the peripheral data recorder from the data processing unit to which it is attached. The desire for high performance and great storage capacity was not satisfied by any of the above solutions.
The Eden, et al, U.S. Pat. No. 3,569,938 shows the concept of a peripheral apparent store characterized as having a high speed storage which operates with the data processing unit and a bulk storage which stores large amounts of data. A control closely associated with the high speed storage and the bulk storage responds to the request from a data processing unit for maintaining data in the high speed storage that is expected to be next used by the data processing unit. This control, called a storage manager, responds to requests from the data processor for paging data from the bulk storage to the high speed storage and in the reverse direction in accordance with predetermined space allocation and replacement rules. In one embodiment the high speed storage was a magnetic core random accessed memory similar to the present day semiconductor memories. The bulk storage can be magnetic disk storage or magnetic tape storage. Also, magnetic disk storage may be a high speed storage for a magnetic tape store. The apparent peripheral store was to provide data and receive data from a plurality of computer connections. The Arnold, et al U.S. Pat. No. 3,670,307 shows a way of improving the operations of a two-level storage hierarchy in that only altered data is moved from the high speed store to the bulk store. Greater flexibility of the apparent store is shown by Amdahl, et al in U.S. Pat. No. 3,670,309 wherein a plurality of ports or host attachment circuits are provided; each port has its own control and has the capability of queuing access requests such that internal operations of the two-level hierarchy is enhanced. Other enhancements of this peripheral storage hierarchy includes placing a data buffer in a channel such as shown in U.S. Pat. No. 3,699,530. This buffer appears to be a first in first out buffer wherein data is queued prior to being assigned to main memory. The variation of a buffer in a channel is shown in U.S. Pat. No. 3,735,360 wherein each processor has its own cache buffer, i.e. rather than a FIFO buffer, a true managed buffer for cache data is provided for each channel. A host attachment for attaching a peripheral storage system to a host is shown in U.S. Pat. No. 3,812,475. Yet another buffered disk storage apparatus is shown in U.S. Pat. No. 3,839,704 how an input/output channel of data processing system accesses data from a disk storage apparatus when a caching buffer is provided. A more elaborate storage hierarchy is shown by Dejohn, et al in U.S. Pat. No. 4,053,752 wherein a plurality of disk storage apparatus cache data from an automatic tape library. Data transfers between a tape library and the caching disk storage apparatus is via a FIFO buffer wherein data is queued in either direction of transfer. A small serializer/deserializer buffer is interposed between the host input/output channel and the caching disk storage apparatus.
The idea of caching in memory also exists between the main memory and a processor. For example, in U.S. Pat. No. 4,189,770 the cache is selectively bypassed on certain operand data transfers. U.S. Pat. No. 4,157,586 shows updating the main memory cache when the back store for main memory is also updated. Transferring data from the cache to the main memory while measuring the rate of accesses to the cache by the processor and then taking time out to do the main memory data transfers shown in U.S. Pat. No. 4,159,517. Caches have been organized in a plurality of caches each having a directory such as shown in U.S. Pat. No. 4,142,234. A copy back control in a multilevel storage hierarchy is shown in U.S. Pat. No. 4,084,231. U.S. Pat. No. 4,020,466 shows copying back to lower levels all changes in upper levels of storage. U.S. Pat. No. 3,588,839 shows moving altered data from a high level in the storage hierarchy to a lower level as soon as possible.
Peripheral systems traditionally attach to various types of computers. Rather than redesign attachments for each type of computer, so-called channels have been developed which couple diverse computers to diverse peripheral systems. With channels, one peripheral system can simultaneously be connected to several different types of computers. It turns out that even with channels, diverse computers have different I/O or channel commands. To accommodate different command sets, the peripheral systems have included diverse circuits. For example, U.S. Pat. No. 3,721,961 shows connecting a peripheral system to diverse computers having diverse command sets. A circuit accommodates the computer diversity by enhancing recovery capabilities of one computer to that of another computer.
Even with all of the above techniques a more optimal performing peripheral storage hierarchy has yet to be devised. Certain improvements in such storage hierarchy internal operations which enhance data integrity as well as providing faster access to the data is still highly desirable. As peripheral devices have increased capability, there is still a requirement that those devices operate with older and probably slower hosts. In particular, input/output or peripheral channel data transfer capacities have substantial data rate variations. For example, a so-called streaming channel can have a capacity for transferring three megabytes per second while older channels may have a capacity of 1.5 megabytes or less per second. Therefore, when new devices are incorporated into a storage hierarchy, it is desired that that hierarchy be capable of attaching not only to the faster channels but also to the slower channels. Such attachments may require substantially diverse data handling techniques for providing an efficient storage hierarchy.